ReMAP is pleased to announce that Jeff Kennedy, SMTA Board President and Technology Director, Celestica will be presenting, NASA‐DoD Phase 3 Consortium Testing Plan for Alternate Alloys for Use on High Reliability Products at SMTA Pan Pacific 2017 in Hawaii. The presentation is scheduled for Tuesday, February 7th, 10:15am.
In addition to the NASA paper, Jeff will be chairing Session 12, Quality and Reliability on Thursday, February 9th as well as the SMTA International Board Meeting.
The SMTA Pan Pacific 2017 Microelectronics Symposium (PanPac) will be held from February 6 to 9 at the Sheraton Poipu Kauai Resort, Hawaii, United States.
The requirements for high reliability products are driving continued study for solutions that will enable Pb-Free product manufacturing while maintaining or improving the reliability of those products in applications and field performance. Several industry sectors require high reliability like Medical, Underground Sensing for gas and oil, Automotive, Aerospace, and Defense. Many applications have not found a suitable solution for Pb-free assembly materials that will meet product requirements needed for high reliability over a long product lifetime.
This paper will present the project plan for the 2017 launch of the NASA-DoD Phase 3 testing of alternate or next generation alloys. The intent of this project is to build on the preliminary research and developments to advance the technology readiness level for the potential use of improved performance alternate alloys. This project study details will be presented and the project plan explained to further the industry awareness of this work in light of parallel alternate alloy studies in progress. Discussion of these other parallel efforts will presented to illustrate how this project will provide the industry with additional reliability data that may further the quest of finding a good solution for Pb-free high reliability products.
Key words: Pb-free, pad cratering, reliability, harsh environments testing, aerospace
About SMTA Pan Pac 2017
The Pan Pacific Microelectronics Symposium provides an opportunity for global experts in microelectronics to present their research, exchange ideas and network with business leaders. The Symposium program includes keynotes and ground-breaking research presentations on materials, reliability, nanotechnology, quality, design & manufacturing strategies, packaging, roadmaps and manufacturing strategies, advanced processes, and embedding & Fan-Out packaging.
Date: February 6-9, 2017
Venue: Sheraton Poipu Kauai Resort
Address: 2440 Hoonani Road, Poipu Beach, Koloa, HI, 96756 USA